FPGA学习-8：简单的时序电路

module Start(
	input clk,
	input button,	
	output[2:0] led
);


reg[31:0] pll,cnt;
reg[2:0] out;

assign led = ~out;

initial begin
	pll = 32'd24000000;
	cnt = 32'd0;	
	out = 3'b001;
end

always @(posedge clk )begin
	if(cnt <= pll) begin
		cnt = cnt + 32'd1;	 
	end		
	else begin	
		cnt = 32'd0;		
		out = out << 1;	
		if(out == 3'd0)begin		
			out = 3'b001;
		end							
		
	end		
end

integer i=1;

always @(posedge button)begin
	case(i)
		1:begin		
			i=2;		
			pll=32'd12000000;
		end			
		2:begin	
			i=3;		
			pll=32'd6000000;
		end			
		3:begin			
			i=1;		
			pll=32'd24000000;
		end		
	
	endcase

end	

endmodule

module Mul(
	input clk, //时钟信号
	input rst,	//复位信号
	output reg flag,//是否完成信号
	input[7:0] Ai, 
	input[7:0] Bi, 
	output reg[15:0] result
);	

reg[15:0] bi;

initial begin
	bi = {8'd0,Bi};
	flag = 0;	
	result= 0;
end	

integer i=0;

always @(posedge clk or posedge rst) begin
	if(rst == 1)begin
		bi = Bi;
		flag = 0;	
		result = 0;		
		i=0;
	end			
	else if(flag == 0)begin	
		result = result + (Ai[i] ? bi:0);
		bi = bi << 1;		
		i = i + 1;		
		if(i>=8)begin		
			flag = 1;
		end	
	end
end	

endmodule